Sowmya K B , Anoop Jali , Jeevottam Heble and Dureen Anand RV College of Engineering, India

The Local Interconnect Network (LIN) is a low-cost serial communication protocol commonly used in automotive electronics and low-speed embedded systems. This paper details the design, implementation, and verification of a LIN controller that meets the LIN 2.x specification. The proposed architecture adopts a modular approach, including master and slave nodes, synchronization logic, checksum calculation, and frame buffering. The controller does not rely on standard UART peripherals. Instead, it uses custom bit-level transmission and reception logic to provide reliable communication. Functional verification is done using Verilog testbenches and internal loopback setups, followed by synthesis and hardware validation on the DE0-Nano FPGA. Simulation and hardware results demonstrate accurate frame generation, synchronization, identifier decoding, and checksum verification at 19.2 kbps. The design delivers a resource-efficient and fully synthesizable LIN controller that is well-suited for low-cost automotive and industrial applications

Local Interconnect Network (LIN), FPGA, Automotive Communication, Master–Slave Architecture, SoC (System on Chip Design).